The invention relates to technology for implementing electronic design automation tools, and in particular, design tools for performing parallel and multithreaded design rule checks (DRC) for an integrated circuit (“IC”) design.
An IC is a small electronic device typically formed from semiconductor material. Each IC contains a large number of electronic components, e.g., transistors, that are wired together to create a self-contained circuit device. The components and wiring on the IC are materialized as a set of geometric shapes that are placed and routed on the chip material. During placement, the location and positioning of each geometric shape corresponding to an IC component are identified on the IC layers. During routing, a set of routes are identified to tie together the geometric shapes for the electronic components.
A set of design rules are established to ensure that the objects/shapes on the IC design can be properly manufactured. These rules are usually established by the foundry that will produce the IC chip. A DRC tool is used to check for violations of the rules on the IC design.
Given the large numbers of components in a typical IC design and the large number of rules that must be checked, it often takes a long period of time and a significant amount of system resources (both for CPU and memory) to perform a DRC check on a given IC design. This provides the motivation for EDA tool vendors to provide a method for parallelizing the DRC operations that must be performed against an IC design.
Solutions have been proposed to partition data for DRC operations to allow parallelization of the DRC process. There have been several suggested approaches for data partitioning. A first approach is partitioning based upon the rules and a second approach is based on hierarchy. Conventionally, these are mutually exclusive approaches, and while there is some efficiency in each one of them, these are also problems with each approach.
When data partitioning is performed based on rules, one of the most significant problems is that network jamming may occur. This is because the entire design file (e.g., a GDSII file) is sent to each distributed computer that is processing in parallel based upon the rules. This means that there is a lot of traffic being placed on the network.
The other approach is to partition the design using a hierarchy where the system sends different blocks affecting the design from one distributed processing unit to another. The problem with data partitioning using this approach is that when the system is trying to verify the top level, problems dealing with the connectivity between the blocks may exist. Conventional systems cannot efficiently or optimally manage this type of problem.
There may also exist other proposed approaches, such as windowing. However, these other approaches are also mutually exclusive approaches, and while there is some efficiency in each one of them, there are also problems with each approach.
Therefore, it is highly desirable to implement an improved method and mechanism for data partitioning for a DRC tool that will efficiently and effectively allow parallelization and multithreading to occur for DRC analysis of the IC design. Some embodiments of the invention provide an improved method and mechanism for data partitioning for a DRC tool that allows parallelization and multithreading to occur for DRC analysis of the IC design. Data partitioning is performed in some embodiments to allow some of the data to be processed in parallel by distributed processing units, while allowing other of the data to be processed in parallel by multiple threads. This can be accomplished by identifying different types of rules and data, and having different types of processing for the different types of rules and data. Certain types of rules/data will be processed with multi-threaded processing and other types of rules/data will be processed in parallel using distributed processing units.